isp1563 NXP Semiconductors, isp1563 Datasheet - Page 45

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 55.
Address: Content of the base address register + 18h
[1]
Table 56.
Address: Content of the base address register + 18h
Table 57.
Address: Content of the base address register + 1Ch
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
HCCA[23:0]
reserved
HcHCCA - Host Controller Communication Area register bit allocation
HcHCCA - Host Controller Communication Area register bit description
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation
11.1.8 HcPeriodCurrentED register
R/W
R/W
R/W
R/W
31
23
15
31
23
R
R
0
0
0
7
0
0
0
minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0
when read. This area is used to hold control structures and the interrupt table that are
accessed by both the Host Controller and the HCD.
The HcPeriodCurrentED register contains the physical address of the current isochronous
or interrupt ED.
Description
Host Controller Communication Area Base Address: This is the base address of the HCCA.
-
R/W
R/W
R/W
R/W
30
22
14
30
22
R
R
0
0
0
6
0
0
0
Table 57
R/W
R/W
R/W
R/W
29
21
13
29
21
R
R
0
0
0
5
0
0
0
Rev. 02 — 15 March 2007
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
28
20
12
28
20
R
R
0
0
0
4
0
0
0
HCCA[23:16]
PCED[27:20]
PCED[19:12]
HCCA[15:8]
HCCA[7:0]
reserved
[1]
R/W
R/W
R/W
R/W
27
19
11
27
19
R
R
0
0
0
3
0
0
0
R/W
R/W
R/W
R/W
26
18
10
26
18
R
R
0
0
0
2
0
0
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
25
17
R
R
0
0
9
0
1
0
0
0
© NXP B.V. 2007. All rights reserved.
ISP1563
R/W
R/W
R/W
R/W
45 of 102
24
16
24
16
R
R
0
0
8
0
0
0
0
0