isp1563 NXP Semiconductors, isp1563 Datasheet - Page 63

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 90.
Address: Content of the base address register + 100h
Table 91.
Address: Content of the base address register + 104h
[1]
Table 92.
Address: Content of the base address register + 104h
ISP1563_2
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 0
The reserved bits should always be written with the reset value.
HceControl - Host Controller Emulation Control register bit description
HceInput - Host Controller Emulation Input register bit allocation
HceInput - Host Controller Emulation Input register bit description
Symbol
reserved
IN_DATA[7:0]
Symbol
C_P
EI
EE
11.2.2 HceInput register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
The HceInput register is a 4-byte register, and the bit allocation is given in
I/O data that is written to ports 60h and 64h is captured in this register, when emulation is
enabled. This register may directly be read or written by accessing it in the Host
Controller’s operational register space. When directly accessed in a memory cycle, reads
and writes of this register have no side effects.
Description
Character Pending: When this bit is set, an emulation interrupt is generated when OUT_FULL
is set to logic 0.
Emulation Interrupt: This bit shows the emulation interrupt condition.
0 — Legacy emulation enabled
1 — Legacy emulation disabled
Emulation Enable: When this bit is set to logic 1, the Host Controller is enabled for legacy
emulation. The Host Controller decodes accesses to I/O registers 60h and 64h, and enables
interrupts on IRQ1 or IRQ12, or both. The Host Controller also generates an emulation
interrupt at appropriate times to invoke the emulation software.
Description
-
Input Data: This register holds data that is written to I/O ports 60h or 64h.
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 15 March 2007
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
IN_DATA[7:0]
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
…continued
0
0
0
2
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
Table
91. The
R/W
R/W
R/W
R/W
63 of 102
24
16
0
0
8
0
0
0