tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 116

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tmp88fw45afg

Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
10.3
Function
10.3.4
Table 10-3 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz)
edges respectively selected with the CTC1CR1<CTC1SE> and CTC1CR1<CTC1E>). The source clock is an
internal clock. When matched with the CTC1DR A/B/C Registers, the timer output F/F corresponding to each
mode is inverted. When matched with the CTC1DR A/B/C Registers next time, the timer output F/F is inverted
again. An INTCTC1 interrupt request is generated when the counter value matches the maximum register value
set by CTC1CR2<CTCREG>. The timer output F/F is cleared to 0 when reset. Because CTC1CR2<CTC1FF0>
can be used to set the initial value for the timer output F/F, an active-high or active-low pulse whichever is desired
can be output. The CTC1DRB and CTC1DRC Registers cannot be accessed for write unless they are set for PPG
output mode and the registers used are selected with CTC1CR2<CTC1REG>. The number of registers set can
be altered during operation. In this case, however, be sure to set the number of registers used and write values to
the data registers before the next CTC1INIT1 is output after the first CTC1INIT1 output. Even when only altering
the data register values while leaving the number of registers unchanged, be sure to do this within the same period
of time.
CTC1CK
The timer/counter starts counting as a command or edge on CTC pin input (rising/falling edge and one/both
Programmable Pulse Generate (PPG) output mode
000
001
010
011
100
101
110
Note:When Port P47 is set as a CTC input port, an edge input resets the timer/counter. when PPG output
mode is selected and external trigger start is not used, set CTC1CR2<EXTRGDIS> to "1" or set P47 as
an output port.
Table 10-2 External Clock Source for Compare Timer/Counter 1
Maximum applied frequency [Hz]
Resolution [μs]
Minimum pulse width
0.2
0.1
DV1CK = 0
Maximum Setting Time [s]
13.11 m
6.55 m
Page 102
NORMAL and IDLE Modes
NORMAL and IDLE Modes
2
2
Up to fc/2
/fc and over
Resolution [μs]
0.2
2
DV1CK = 1
Maximum Setting Time [s]
13.11m
TMP88FW45AFG

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