tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 23

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tmp88fw45afg

Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
2. Functional Description
2.1
2.1.1
Functions of the CPU Core
The CPU core consists mainly of the CPU, system clock control circuit, and interrupt control circuit.
This chapter describes the CPU core, program memory, data memory, and reset circuit of the TMP88FW45AFG.
and DBR/EBR (Data Buffer Registers), which are mapped into one 1-Mbyte address space. The general-purpose
registers consist of 16 banks, which are mapped into the RAM address space. Figure 2-1 shows a memory address
map of the TMP88FW45AFG.
ROM: Read-Only Memory
RAM: Random Access Memory
Memory Address Map
The memory of the TMP88FW45AFG consists of four blocks: ROM, RAM, SFR (Special Function Registers),
ROM
(
RAM
(
DBR/EBR
SFR
RAM
(128 bytes)
120K
Program memory
Vector Table
Data memory
Stack
General-purpose register bank
4K
bytes)
bytes)
21EFFH
FFFFFH
000BFH
000C0H
01FFFH
FFF00H
FFF3FH
FFF40H
FFF7FH
FFF80H
0003FH
010BFH
00000H
00040H
04000H
01F70H
122624
4096
SFR: Special Function Registers
144
128 bytes
128 bytes
64 bytes
64 bytes
64 bytes
Figure 2-1 Memory address map
bytes
bytes
bytes
Input/output port
Peripheral hardware control register
Peripheral hardware status register
System control register
Interrupt control register
Program status word
Special Function Register
General-purpose Register Bank
(8 registers × 16 banks)
Random-Access Memory
Data Buffer Register
(peripheral hardware control register / status register)
Program Memory
Interrupt Vector Table
Vector Table for
Vector Call Instructions
Interrupt Vector Table
Page 9
DBR: Data Buffer Registers
EBR: Extra Data Buffer Registers
Input/output port
Peripheral hardware control register
Peripheral hardware status register
Input/output port
Peripheral hardware control register
Peripheral hardware status register
TMP88FW45AFG

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