tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 221

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.6.3
DBR
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SI pin
INTSIO Interrupt
interrupt service program.
the receiving is ended at the time that the final bit of the data has been received. That the receiving has ended can
be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiving is ended.
After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIOINH> is set, the
receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is ignored, and it is not
required to be read out.)
to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”. If it
is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after
completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read out.
to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”. When
transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving, the data
are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit data are
transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when the number
of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive data from the
buffer register in the interrupt service. The data buffer register is used for both transmitting and receiving; there-
fore, always write the data to be transmitted after reading the all received data.
are written. A wait will not be initiated if even one transfer data word has been written.
necessary to read the received data and write the data to be transmitted next before starting the next shift operation.
When an external clock is used, the transfer speed is determined by the maximum delay between generation of
an interrupt request and the received data are read and the data to be transmitted next are written.
Figure 17-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS> cleared,
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be cleared
After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first
When the internal clock is used, a wait is initiated until the received data are read and the next transfer data
When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is
8-bit transfer / receive mode
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch
the transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch
the transfer mode.
a
0
a
1
a
2
a
3
a
4
Page 207
a
5
a
6
a
7
Read out
a
b
0
b
1
b
2
Clear SIOS
b
3
b
4
b
TMP88FW45AFG
5
b
6
b
7
Read out
b