tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 37

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.1.5
2.1.5.1
2.1.5.2
timer reset , system clock reset and oscillation frequency detection reset.
reset) are not initialized.
Table 2-3 Internal Hardware Initialization by Reset Operation
Reset Circuit
The TMP88FW45AFG has five ways to generate a reset: external reset input, address trap reset, watchdog
Table 2-3 shows how the internal hardware is initialized by reset operation.
At power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock
Program Counter (PC)
Stack Pointer (SP)
General-purpose Registers
(W, A, B, C, D, E, H, L)
Register Bank Selector (RBS)
Jump Status Flag (JF)
Zero Flag (ZF)
Carry Flag (CF)
Half Carry Flag (HF)
Sign Flag (SF)
Overflow Flag (VF)
Interrupt Master Enable Flag (IMF)
Interrupt Individual Enable Flag (EF)
Interrupt Latch (IL)
Interrupt Nesting Flag (INF)
at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operating
voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initialized.
program beginning with the vector address stored at addresses FFFFCH to FFFFEH.
RAM,SFR or DBR/EBR area, the device generates an internal reset.
The address trap is permitted initially and the internal reset is generated by fetching from internal RAM,SFR
or DBR/EBR area. If the address trap is prohibited, instructions in the internal RAM area can be executed.
The RESET pin is a hysteresis input with a pull-up resistor included. By holding the RESET pin low for
When the RESET pin input is released back high, the device is freed from reset and starts executing the
If the CPU should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal
The address trap permission/prohibition is set by the address trap reset control register (ATAS,ATKEY).
External Reset Input
Address Trap Reset
Internal Hardware
RESET
Figure 2-12 Reset Circuit
(FFFFEH to FFFFCH)
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Initial Value
0
1
0
0
0
0
VDD
Page 23
Prescaler and divider for the
timing generator
Watchdog timer
Output latch of input/output port
Control register
RAM
Internal Hardware
Reset input
See description of
each input/output
port.
See description of
each control
register.
Not initialized
Initial Value
Enable
TMP88FW45AFG
0