tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 130

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12.3
Function
Example :Generating 1024 Hz pulse (fc = 20.0 MHz and CGCR<DV1CK> = 0)
12.3.4
low, the duty pulse may be shorter than the programmed value.
resolution by an internal clock.
PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the
PWM4 pin becomes high. The INTTC4 interrupt request is generated at this time.
low, one PMW cycle may be shorter than the programmed value.
to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically.
For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR<TC4S> to 1.
Internal clock
Counter
TC4DR
Timer F/F
PDO4 pin
INTTC4 interrupt
request
Note 1: The PWM output mode can be used only in the NORMAL and IDEL modes.
Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated
When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is
The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of
When a match between the up-counter and the TC4DR value is detected, the logic level output from the
When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is
TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set
Pulse Width Modulation (PWM) Output Mode
(typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt
occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the
programmed value until the next INTTC4 interrupt request is issued.
LD
SET
LD
LD
0
n
1
Match detect
Figure 12-2 PDO Mode Timing Chart
2
(TC4CR), 00000110B
(P2DR), 2
(TC4DR), 4CH
(TC4CR), 00100110B
n 0
1
Page 116
2
: Sets the PDO mode. (TC4M = 10, TC4CK = 001)
: Sets the P22 output latch to 1.
: 1/1024 ÷ 2
: Start TC4
n 0
1
7
/fc ÷ 2 (half cycle period) = 4CH
2
n 0
1
2
TMP88FW45AFG
n 0
1