tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 81

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example : 2.44 kHz pulse output (fc = 20.0 MHz)
6.2
Time Base Timer Control Register
buzzer drive. Divider output is from DVO pin.
Divider Output (DVO)
(00036H)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
The Divider Output is controlled by the Time Base Timer Control Register (TBTCR).
Note 1: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
Note 2: In case of using DVO output, set output mode by P1CR register after setting the related port output latch to "1" by P1DR
Note 3: fc; High-frequency clock [Hz], *; Don't care
Note 4: Be sure to write "0" to TBTCR Register bit 4.
TBTCR
Data output
fc/2
fc/2
fc/2
fc/2
13
12
11
10
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do
not change the setting of the divider output frequency.
register.
,fc/2
,fc/2
,fc/2
,fc/2
DVOEN
14
13
12
11
Divider output control register
DVOCK
7
(a) configuration
DVOEN
DVOCK
LD
LD
Output latch
A
B
C
D
D
MPX
2
S
Y
TBTCR
Q
6
Divider output
enable / disable
Divider Output (DVO)
frequency selection: [Hz]
DVOCK
Port setting
(TBTCR) , 00000000B
(TBTCR) , 10000000B
DVOEN
5
Figure 6-3 Divider Output
"0"
4
Page 67
(TBTEN)
DVO pin
3
0: Disable
1: Enable
00
01
10
11
Port output latch
TBTCR<DVOEN>
DVO pin output
; DVOCK ← "00"
; DVOEN ← "1"
2
DV1CK=0
(TBTCK)
fc/2
fc/2
fc/2
fc/2
1
13
12
11
10
(b) Timing chart
NORMAL, IDLE Mode
0
(Initial value: 0000 0000)
DV1CK=1
TMP88FW45AFG
fc/2
fc/2
fc/2
fc/2
14
13
12
11
R/W
R/W