tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 219

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
INTSIO interrupt
DBR
Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request
to writing of the data to the data buffer register by the interrupt service program.
empty interrupt service program.
is cleared to “0” when a transfer is completed.
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Figure 17-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
When an external clock is used, the data must be written to the data buffer register before shifting next data.
The transmission is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to “0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
Write
(a)
a
Write
a
(b)
0
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a
6
a
7
b
0
b
1
b
Clear SIOS
2
b
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b
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b
5
TMP88FW45AFG
b
6
b
7