tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 171

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

MDCRA
DTR
MDOUT
E, D, C
3, 2
7, 6
5, 4
3, 2
1, 0
B
A
7
6
5
4
1
0
F
9
8
MDPRD
MDCNT
CMPW
CMPU
CMPV
DTR
PWMMD
PWMEN
UPDWN
HLFINT
DTYMD
PDEXP
PSYNC
WPWM
SYNCS
UPWM
VPWM
POLH
POLL
WOC
PINT
VOC
UOC
Dead time
PWM counter
Set PWM period
Set PWM pulse width
Select half-period interrupt
DUTY mode
Upper-phase port polarity
Lower-phase port polarity
PWM interrupt frequency
PWM mode
Enable/Disable waveform
generation circuit
PWM counter flag
Mode compare register
Select PWM synchronization
Control UVW-phase PWM
outputs
Select port output sync signal
Control UVW-phase outputs
When this bit is set to 1, INTPWM is generated every half period (at triangular wave peak
and valley) in the case of center PWM output and PINT = 00. In other cases, this setting
has no meaning.
Select whether to set the duty cycle independently for three phases using the CMPU to W
Registers or in common for all three phases by setting the CMPU Register only.
Select the upper-phase output port polarity. Make sure the waveform synthesis function
(MDCRA Register bit 0) is idle before selecting this port polarity.
Select the lower-phase output port polarity. Make sure the waveform synthesis function
(MDCRA Register bit 0) is idle before selecting this port polarity.
Select the frequency at which to generate a PWM interrupt from four choices available:
every PWM period or once every 2, 4, or 8 PWM periods. When setting of this bit is altered
while operating, an interrupt may be generated at the time the bit is altered.
Select PWM mode. PWM mode 0 is an edge PWM (sawtooth wave), and PWM mode 1 is
a center PWM (triangular wave).
When enabling this circuit (for waveform output), be sure to set the output port polarity and
other bits of this register (other than MDCRA bit 0) beforehand.
Set the dead time between the upper-phase and lower-phase outputs.
This bit indicates whether the PWM counter is counting up or down. When edge PWM
(sawtooth wave) is selected, it is always set to 0.
Set the data to be compared with the position detection input port. The comparison data is
adopted as the expected value simultaneously when port output sync settings made with
MDOUT are reflected in the ports.
(This is the expected position detection input value for the output set with MDOUT next
time.)
Select whether or not to synchronize port output to PWM period after being synchronized
to the synchronizing signal selected with SYNCS. If selected to be synchronized to PWM,
output is kept waiting for the next PWM after being synchronized with SYNCS. Waveform
settings are overwritten if new settings are written to the register during this time, and output
is generated with those settings.
Set U, V, and W-phase port outputs. (See the Table 14-3)
Select the synchronizing signal with which to output UVW-phase settings to ports. The
synchronizing signal can be selected from Timers 1 or 2, position detection, or asynchro-
nous. Select asynchronous when the initial setting, otherwise the above setting isn’t
reflected immediately.
Set U, V, and W-phase port outputs. (See the Table 14-3)
This is a 12-bit read-only register used to count PWM periods.
This register determines PWM period, and is dual-buffered, allowing PWM period to be
altered even while the PWM counter is operating. The buffers are loaded every PWM pe-
riod. When 100 ns is selected for the PWM counter clock, make sure the least significant
bit is set to 0.
This comparison register determines the pulse widths output in the respective UVW pha-
ses. This register is dual-buffered, and the pulse widths are determined by comparing the
buffer and PWM counter.
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TMP88FW45AFG