tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 72

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.8
Port P7 (P77 to P70)
5.8
Note 1: i = 7 to 0
Note 2: STOP exists in SYSCR1 register bit 7.
Note 3: SAIN selects AD input channel.
Note 4: OFDRST shows a reset signal of oscillation frequency detection.
and output modes using the P7 port input/output control register (P7CR), P7 port output latch (P7DR), and ADC-
CRA<AINDS>. When reset, the P7CR register and the P7DR output latch are initialized to 0 while ADC-
CRA<AINDS> is set to 1, so that P77 to P70 have their inputs fixed low (= 0). When using the P7 port as an input
port, set the corresponding bits for input mode (P7CR = 0, P7DR = 1). The reason why the output latch = 1 is because
it is necessary to prevent current from flowing into the shared data input circuit. When using the port as an output port,
set the P7CR Register's corresponding bits to 1. When using the port for analog input, set the corresponding bits for
analog input (P7CR = 0, P7DR = 0). Then set ADCCRA<AINDS> = 0, and AD conversion will start.
AD conversion are selected using ADCCRA<SAIN>.
instructions on these ports during AD conversion. This is necessary to maintain the accuracy of AD conversion. Also,
do not apply rapidly changing signals to ports adjacent to analog input during AD conversion.
the oscillation frequency detection reset and Port P7 becomes high impedance.
Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port shared with AD converter analog input. This port is switched between input
The ports used for analog input must have their output latches set to 0 beforehand. The actual input channels for
Although the bits of P7 port not used for analog input can be used as input/output ports, do not execute output
If an input instruction is executed while the P7DR output latch is cleared to 0, data “0” is read in from said bits.
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
Data output (P7)
Data input (P7)
Analog input
P7CRi input
OFDRST
OUTEN
AINDS
P7CRi
STOP
SAIN
D
D
Q
Q
Figure 5-9 Port P7
Page 58
P7i
TMP88FW45AFG