tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 61

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.2
P1 Port Input/Output Registers
(00001H)
(0000BH)
Table 5-2
Note 1: i = 7 to 0
Note 2: OFDRST shows a reset signal of oscillation frequency detection.
output. This port is switched between input and output modes using the P1 port input/output control register (P1CR).
When reset, the P1CR register is initialized to 0, with the P1 port set for input mode. Also, the output latch (P1DR) is
initialized to 0 when reset.
the oscillation frequency detection reset and Port P1 becomes high impedance.
P1DR
P1CR
Port P1 (P17 to P10)
Port P1 is an 8-bit input/output port shared with external interrupt input, timer/counter input/output, and divider
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P1ODE
Note 1: TC5O: PDO5, PWM5
0
0
0
0
1
1
1
1
PDW2
P17
P1CR
7
7
P1CR
0
0
1
1
0
0
1
1
Control output
PDV2
P16
Control input
6
6
Data output
P1 port input/output control
(Specify bit wise)
Data input
OFDRST
P1ODEi
OUTEN
P1CRi
STOP
PDU2
P15
P1DR
5
5
0
1
0
1
0
1
0
1
PPG1
TC5O
Output latch
P14
4
4
Data input (by reading instruction)
D
Input Data from port (Low)
Input Data from port (Low)
Figure 5-3 Port P1
"0" (output latch data)
"1" (output latch data)
Q
Input Data from port
Input Data from port
Input Data from port
Input Data from port
DVO
TC5I
P13
0: Input mode
1: Output mode
3
3
Page 47
INT2
TC1
P12
2
2
INT1
P11
1
1
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
INT0
Control input
P10
0
0
Read/Write
(Initial value: 0000 0000)
TC5O: PDO5, PWM5
(Initial value: 0000 0000)
P1i
TMP88FW45AFG
Output data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"
R/W