tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 141

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.3.4
counter counts up using the internal clock.
F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/
Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj
interrupt request is generated at this time.
generated. Upon reset, the timer F/Fj is cleared to 0.
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the INTTCj
interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediately after the
programming of PWREGj. If executing the read instruction to PWREGj during PWM output, the value in the
shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the reading data of
PWREGj is previous value until INTTCj is generated.
Table 13-4 PWM Output Mode
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
Note 4: j = 5, 6
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-
When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6)
DV1CK = 0
fc/2
fc/2
fc/2
fc/2
11
NORMAL, IDLE mode
[Hz]
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt
request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different
from the programmed value until the next INTTCj interrupt request is generated.
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PWMj pin to the high level.
mode is entered without stopping the timer when fc or fc/2 is selected as the source clock, a pulse is output
from the PWMj pin during the warm-up period time after exiting the STOP mode.
7
5
3
Source Clock
DV1CK = 1
fc/2
fc/2
fc/2
fc/2
12
[Hz]
8
6
4
fc = 20 MHz
DV1CK = 0
102.4 μs
6.4 μs
1.6 μs
0.4 μs
Page 127
Resolution
fc = 20 MHz
DV1CK = 1
204.8 μs
12.8 μs
3.2 μs
0.8 μs
fc = 20 MHz
DV1CK = 0
26.21 ms
1.64 ms
410 μs
102 μs
Repeated Cycle
fc = 20 MHz
DV1CK = 1
52.43 ms
3.28 ms
819 μs
205 μs
TMP88FW45AFG