tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 144

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.3
Function
13.3.6
13.3.7
TC6CR<TC6S>
TTREG5
(Lower byte)
TTREG6
(Upper byte)
INTTC6 interrupt request
Internal
source clock
Counter
and 6 are cascadable to form a 16-bit event counter.
timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is cleared.
machine cycles are required for the low- or high-level pulse input to the TC5 pin.
lower byte (TTREG5), and upper byte (TTREG6) in this order in the timer register. (Programming only the upper
or lower byte should not be attempted.)
TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator.
level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level
output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the counter is
cleared. The INTTC6 interrupt is generated at this time.
frequency to be supplied is fc/2
generated. Upon reset, the timer F/F6 is cleared to 0.
and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of the timer are
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
Note 3: j = 5, 6
In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC5 pin. Two
Therefore, a maximum frequency to be supplied is fc/2
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic
Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum
Since the initial value can be set to the timer F/F6 by TC6CR<TFF6>, positive and negative pulses can be
(The logic level output from the PWM6 pin is the opposite to the timer F/F6 logic level.)
Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to PWREG6
16-Bit Event Counter Mode (TC5 and 6)
16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)
Figure 13-6 16-Bit Timer Mode Timing Chart (TC5 and TC6)
pulses.
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an
expected operation may not be obtained.
?
?
0
n
m
1
2
4
Hz in the NORMAL1 or IDLE1 mode.
3
Match
detect
mn-1
Page 130
mn
0
Counter
clear
1
4
Hz in the NORMAL or IDLE mode. Program the
2
Match
detect
mn-1
mn
0
Counter
clear
1
TMP88FW45AFG
2
0