tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 178
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tmp88fw45afg
Manufacturer Part Number
tmp88fw45afg
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88FW45AFG.pdf
(294 pages)
- Current page: 178 of 294
- Download datasheet (4Mb)
14.5
Three-phase PWM Output Unit
EMGCRB
(01FB1H)
(01FE1H)
EMGCRA
(01FB0H)
(01FE0H)
Note:If during overload protection the port output state in two or more upper phases is on, all lower phases are disabled
Note 1: An instruction specifying a return from the EMG state is invalid if the EMG input is “L”.
Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGCRB or EMGCRA register
and all upper phases are enabled for output; when two or more lower phases are on, all upper phases are disabled
and all lower phases are enabled for output.
7 to 4
3, 2
7
6
5
4
1
0
2
1
0
RTCL
because these registers contain write-only bits.
7
7
RTCL
RTPWM
RTTM1
CLST
CLMD
CNTST
CLEN
CLCNT
EMGST
RTE
EMGEN
RTPWM
6
6
CLCNT
RTTM1
Return from overload protective
state
Enable/Disable return from
overload protective state by
PWM sync
Enable/Disable return from
overload protective state by tim-
er 1
Overload protective state
Select output disabled phases
during overload protection
Stop PWM counter during over-
load protection
Enable/Disable overload pro-
tective circuit
Overload protection sampling
number of times.
EMG protective state
Return from EMG state
Enable/Disable EMG protective
circuit
5
5
CLST
4
4
3
3
CLMD
Page 164
EMGST
0: No operation
1: Return from protective state
0: Disable
1: Enable
0: Disable
1: Enable
0: No operation
1: Under protection
00: No phases disabled against output
01: All phases disabled against output
10: PWM phases disabled against output
11: All upper/All lower phases disabled against output (Note)
0: Do not stop
1: Stop the counter
0: Disable
1: Enable
2
0: No operation
1: Under protection
0: No operation
1: Return from protective state (Note 1)
0: Disable
1: Enable
2
/fc × n ( n = 1 to 15, 0 and 1 are set as 1 at 20 MHz )
2
2
CNTST
RTE
1
1
EMGEN
CLEN
0
0
(Initial value: 0000 0000)
(Initial value: 0000 *001)
TMP88FW45AFG
R/W
R/W
R/W
R/W
W
W
R
R
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