tmp88fw45afg TOSHIBA Semiconductor CORPORATION, tmp88fw45afg Datasheet - Page 59

• Manufacturer Part Number: tmp88fw45afg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.1
Table 5-1
Note 1: i = 3 to 0
Note 2: OFDRST shows a reset signal of oscillation frequency detection.
and output modes using the P0 port input/output control register (P0CR). When reset, the P0CR register is initialized
to 0, with the P0 port set for input mode. Also, the output latch (P0DR) is initialized to 0 when reset.
is used to select open-drain or tri-state mode for the port. When reset, the P0ODE register is initialized to 0, with tri-
state mode selected for the port.
the oscillation frequency detection reset and Port P0 becomes high impedance.
Port P0 (P03 to P00)
Port P0 is a 4-bit input/output port shared with serial interface input/output. This port is switched between input
The P0 port contains bit wise programmable open-drain control. The P0 port open-drain control register (P0ODE)
If high frequency oscillation stops or becomes abnormal in NORMAL/IDLE mode, the TMP88FW45AFG generates
P0ODE
0
0
0
0
1
1
1
1
Control output
Control input
P0CR
Data output
0
0
1
1
0
0
1
1
Data input
OFDRST
P0ODEi
OUTEN
P0CRi
STOP
P0DR
0
1
0
1
0
1
0
1
Output latch
D
Data input (by reading instruction)
Input Data from port (Low)
Input Data from port (Low)
Figure 5-2 Port P0
Q
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Page 45
Input Data from port (Low)
Input Data from port (Low)
"0" (output latch data)
"1" (output latch data)
Input Data from port
Input Data from port
Input Data from port
Input Data from port
Control input
TMP88FW45AFG
Output data
P0i
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"0"
"1"
"0"
"0"