MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 124
MC68HC08AZ60ACFU
Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC08AZ60ACFU.pdf
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System Integration Module (SIM)
8.4.2.1 Power-On Reset
Advance Information
124
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
•
•
•
•
•
•
CYCLES
4096
A POR pulse is generated
The internal reset signal is asserted
The SIM enables CGMOUT
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow the oscillator to stabilize
The RST pin is driven low during the oscillator stabilization time
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared
Figure 8-6. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
$FFFE
MC68HC08AZ60A — Rev 0.0
$FFFF
MOTOROLA
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