MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 303

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
18.9.5 TIMB Channel Registers
MC68HC08AZ60A — Rev 0.0
MOTOROLA
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIMB counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA 0:0) writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares and
the CHxF bit until the low byte (TBCHxL) is written.
PTEx/TCHx
CHxMAX
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 18-8
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
Timer Interface Module B (TIMB)
COMPARE
shows, the CHxMAX bit takes effect in the cycle after it
PERIOD
OUTPUT
Figure 18-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer Interface Module B (TIMB)
OVERFLOW
Advance Information
COMPARE
OUTPUT
I/O Registers
OVERFLOW
303

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