MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 202

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
External Interrupt Module (IRQ)
15.4 Functional Description
Advance Information
202
IRQ
DECODER
VECTOR
FETCH
ACK
A ‘0’ applied to any of the external interrupt pins can latch a CPU
interrupt request.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following occurs:
The external interrupt pin is falling-edge-triggered and is software-
configurable to be both falling-edge and low-level-triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
Figure 15-1. IRQ Module Block Diagram
V
MODE
DD
Vector fetch — a vector fetch automatically generates an interrupt
acknowledge signal which clears the latch that caused the vector
fetch.
Software clear — software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic ‘1’ to the ACK bit clears the
IRQ latch.
Reset — a reset automatically clears the interrupt latch.
D
LATCH
CK
CLR
IRQ
External Interrupt Module (IRQ)
Q
Figure 15-1
IMASK
shows the structure of the IRQ module.
SYNCHRO-
VOLTAGE
DETECT
NIZER
HIGH
MC68HC08AZ60A — Rev 0.0
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
MOTOROLA

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