MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 169

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC08AZ60A — Rev 0.0
MOTOROLA
NOTE:
SSREC — Short Stop Recovery Bit
COPRS — COP Rate Select
STOP — STOP Enable Bit
COPD — COP Disable Bit
Extra care should be taken when selecting MOR options since not all
HC08 family devices have the same options. In particular refer to the
appendix on differences of previous versions of MC68HC08AZ60. It is
the user’s responsibility to correctly define the mask option registers.
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
If using an external crystal oscillator, the SSREC bit should not be set.
COPRS is similar to COPL (please note that the logic is reversed) as
it determines the timeout period for the COP.
STOP enables the STOP instruction.
COPD disables the COP module. See Computer Operating
Properly (COP).
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
1 = COP timeout period is 2
0 = COP timeout period is 2
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Mask Options
13
18
— 2
— 2
4
4
CGMXCLK cycles.
CGMXCLK cycles.
Functional Description
Advance Information
Mask Options
169