MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 158
MC68HC08AZ60ACFU
Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC08AZ60ACFU.pdf
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Clock Generator Module (CGM)
Advance Information
158
NOTE:
NOTE:
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
f
147, and
be written when the PLLON bit in the PLL control register (PCTL) is
set. See
$0 in the VCO range select bits disables the PLL and clears the BCS
bit in the PCTL. (See
Special Programming Exceptions
information.) Reset initializes the bits to $6 to give a default range
multiply value of 6.
VRS
MUL7:MUL6:MUL5:MUL4
. (See
Table 9-3. VCO Frequency Multiplier (N) Selection
Clock Generator Module (CGM)
Special Programming Exceptions
PLL Control Register
Circuits
0000
0001
0010
0011
1101
1110
1111
on page 143,
Base Clock Selector Circuit
on page 153.) VRS7–VRS4 cannot
Programming the PLL
VCO Frequency Multiplier (N)
on page 149 for more
MC68HC08AZ60A — Rev 0.0
on page 149. A value of
13
14
15
1
1
2
3
on page 149 and
MOTOROLA
on page
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