MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 155

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.6.2 PLL Bandwidth Control Register
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Address:
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See
PCTL3–PCTL0 — Unimplemented
The PLL bandwidth control register:
Reset:
Read:
Write:
These bits provide no function and always read as logic 1s.
•
•
•
•
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode
Figure 9-5. PLL Bandwidth Control Register (PBWC)
$001D
AUTO
Bit 7
0
Clock Generator Module (CGM)
9.4.3
= Unimplemented
LOCK
6
0
on page 149.
ACQ
5
0
XLD
4
0
3
0
0
Clock Generator Module (CGM)
2
0
0
Advance Information
CGM Registers
1
0
0
Bit 0
0
0
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