MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 191

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

13.4 I/O Signals
13.4.1 CGMXCLK
13.4.2 STOP Instruction
MC68HC08AZ60A — Rev 0.0
MOTOROLA
NOTE:
NOTE:
MORA. When COPRS = 0, a 4.9152 MHz crystal, gives a COP timeout
period of 53.3ms. Writing any value to location $FFFF before overflow
occurs prevents a COP reset by clearing the COP counter and stages 4
through 12 of the prescaler.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR). See SIM Reset Status
Register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
CGMXCLK is the crystal oscillator output signal. The CGMXCLK
frequency is equal to the crystal frequency.
The STOP instruction clears the COP prescaler.
Hi
. During the break state, V
Computer Operating Properly (COP)
Hi
on the RST pin disables the COP.
Computer Operating Properly (COP)
Advance Information
Figure
I/O Signals
13-1.
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