MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 193

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

13.5 COP Control Register (COPCTL)
13.6 Interrupts
13.7 Monitor Mode
13.8 Low-Power Modes
13.8.1 WAIT Mode
MC68HC08AZ60A — Rev 0.0
MOTOROLA
COPCTL
$FFFF
Reset:
Read:
Write:
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
or on the RST pin.
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
The COP continues to operate during WAIT mode. To prevent a COP
reset during WAIT mode, the COP counter should be cleared
periodically in a CPU interrupt routine.
Figure 13-2. COP Control Register (COPCTL)
Bit 7
Computer Operating Properly (COP)
6
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
Computer Operating Properly (COP)
3
COP Control Register (COPCTL)
HI
is present on the IRQ pin
2
Advance Information
1
Bit 0
193