XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 101

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.71 Arbiter Time-Out Status Register
April 2007 Revised October 2008
BIT
7:6
5
4
3
2
1
0
The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out
status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value.
See Table 4−45 for a complete description of the register contents.
RESET STATE
BIT NUMBER
FIELD NAME
PCI register offset:
Register type:
Default value:
REQ5_TO
REQ4_TO
REQ3_TO
REQ2_TO
REQ1_TO
REQ0_TO
Section 4.70) is asserted and a PCI bus request time-out is detected, then the request time-out
status bits require a special reset sequence. First, the AUTO_MASK bit must be cleared to
0b. Then, the REQ[5:0]_TO bit will clear after a write-back of 1b.
RSVD
NOTE:If bit 6 (AUTO_MASK) in the arbiter request mask register (offset DDh, see
ACCESS
RCU
RCU
RCU
RCU
RCU
RCU
7
0
Table 4−45. Arbiter Time-Out Status Register Description
R
6
0
Reserved. Returns 00b when read.
Request 5 time-out status
Request 4 time-out status
Request 3 time-out status
Request 2 time-out status
Request 1 time-out status
Request 0 time-out status
0 = No time-out
1 = Time-out has occurred
0 = No time-out
1 = Time-out has occurred
0 = No time-out
1 = Time-out has occurred
0 = No time-out
1 = Time-out has occurred
0 = No time-out
1 = Time-out has occurred
0 = No time-out
1 = Time-out has occurred
5
0
DEh
Read/Clear
00h
4
0
3
0
2
0
1
0
DESCRIPTION
0
0
Classic PCI Configuration Space
SCPS155C
91