XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 111

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.6
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
31:13
11:9
BIT
12†
5:1
8†
7†
6†
0†
Correctable Error Status Register
The correctable error status register reports the status of individual errors as they occur. Software may only
clear these bits by writing a 1b to the desired location. See Table 5−5 for a complete description of the register
contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
REPLAY_TMOUT
REPLAY_ROLL
PCI Express extended register offset:
Register type:
Default value:
FIELD NAME
RX_ERROR
BAD_DLLP
BAD_TLP
RSVD
RSVD
RSVD
31
15
0
0
Table 5−5. Correctable Error Status Register Description
ACCESS
RCU
RCU
RCU
RCU
RCU
R
R
R
30
14
0
0
29
13
Reserved. Returns 000 0000 0000 0000 0000b when read.
Replay timer time-out. This bit is asserted when the replay timer expires for a pending request
or completion that has not been acknowledged.
Reserved. Returns 000b when read.
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over after a pending
request or completion has not been acknowledged.
Bad DLLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the
reception of a DLLP.
Bad TLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the
reception of a TLP.
Reserved. Returns 00000b when read.
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.
0
0
28
12
0
0
27
11
0
0
26
10
0
0
Read-only, Read/Clear
0000 0000h
110h
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
PCI Express Extended Configuration Space
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
SCPS155C
18
0
2
0
17
0
1
0
16
0
0
0
101