XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 104

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.74 Serial IRQ Status Register
94
BIT
BIT
1†
0†
15
14
13
12
11
10
9
8
7
SCPS155C
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ
is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are
defined as edge mode in the serial IRQ edge control register are not reported in this status register. See
Table 4−48 for a complete description of the register contents.
RESET STATE
BIT NUMBER
FIELD NAME
FIELD NAME
IRQ1_MODE
IRQ0_MODE
PCI register offset:
Register type:
Default value:
IRQ15
IRQ14
IRQ13
IRQ12
IRQ10
IRQ11
IRQ9
IRQ8
IRQ7
Table 4−47. Serial IRQ Edge Control Register Description (Continued)
ACCESS
15
ACCESS
0
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RCU
RW
RW
Table 4−48. Serial IRQ Status Register Description
14
0
IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.
IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.
IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.
IRQ 12 asserted. This bit indicates that the IRQ12 has been asserted.
IRQ 11 asserted. This bit indicates that the IRQ11 has been asserted.
IRQ 10 asserted. This bit indicates that the IRQ10 has been asserted.
IRQ 9 asserted. This bit indicates that the IRQ9 has been asserted.
IRQ 8 asserted. This bit indicates that the IRQ8 has been asserted.
IRQ 7 asserted. This bit indicates that the IRQ7 has been asserted.
IRQ 1 edge mode
IRQ 0 edge mode
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
0 = Deasserted
1 = Asserted
13
0
0 = Edge mode (default)
1 = Level mode
0 = Edge mode (default)
1 = Level mode
E4h
Read/Clear
0000h
12
0
11
0
10
0
9
0
8
0
DESCRIPTION
DESCRIPTION
7
0
6
0
5
0
April 2007 Revised October 2008
4
0
3
0
2
0
1
0
0
0