XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 115

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

5.11 Secondary Uncorrectable Error Mask Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
31:14
BIT
13†
12†
11†
10†
9†
8†
7†
6†
5†
3†
2†
1†
4
0
The secondary uncorrectable error mask register controls the reporting of individual errors as they occur.
When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages are
blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5−9 for a complete
description of the register contents.
RESET STATE
RESET STATE
SC_MSTR_ABORT_MASK
BIT NUMBER
BIT NUMBER
DISCARD_TIMER_MASK
MASTER_ABORT_MASK
BRIDGE_ERROR_MASK
TARGET_ABORT_MASK
SERR_DETECT_MASK
PERR_DETECT_MASK
SC_MSG_DATA_MASK
UNCOR_ADDR_MASK
ATTR_ERROR_MASK
UNCOR_DATA_MASK
PCI Express extended register offset:
Register type:
Default value:
SC_ERROR_MASK
FIELD NAME
RSVD
RSVD
RSVD
Table 5−9. Secondary Uncorrectable Error Mask Register Description
31
15
0
0
30
14
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
29
13
R
R
R
0
0
28
12
0
1
Reserved. Returns 00 0000 0000 0000 0000b when read.
Internal bridge error. This mask bit is associated with a PCI-X error and has no effect
on the bridge.
SERR assertion detected
PERR assertion detected
Delayed transaction discard timer expired
Uncorrectable address error
Uncorrectable attribute error. This mask bit is associated with a PCI-X error and has no
effect on the bridge.
Uncorrectable data error
Uncorrectable split completion message data error. This mask bit is associated with a
PCI-X error and has no effect on the bridge.
Unexpected split completion error. This mask bit is associated with a PCI-X error and
has no effect on the bridge.
Reserved. Returns 0b when read.
Received master abort
Received target abort
Master abort on split completion. This mask bit is associated with a PCI-X error and
has no effect on the bridge.
Reserved. Returns 0b when read.
0 = Error condition is unmasked
1 = Error condition is masked (default)
0 = Error condition is unmasked (default)
1 = Error condition is masked
0 = Error condition is unmasked
1 = Error condition is masked (default)
0 = Error condition is unmasked
1 = Error condition is masked (default)
0 = Error condition is unmasked
1 = Error condition is masked (default)
0 = Error condition is unmasked
1 = Error condition is masked (default)
0 = Error condition is unmasked (default)
1 = Error condition is masked
27
11
0
0
26
10
0
1
130h
Read-only, Read/Write
0000 17A8h
25
0
9
1
24
0
8
1
23
0
7
1
DESCRIPTION
PCI Express Extended Configuration Space
22
0
6
0
21
0
5
1
20
0
4
0
19
0
3
1
SCPS155C
18
0
2
0
17
0
1
0
16
0
0
0
105