XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 84

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.52 Link Capabilities Register
74
31:24
23:18
17:15
14:12
11:10
BIT
9:4
3:0
SCPS155C
The link capabilities register indicates the link specific capabilities of the bridge. See Table 4−28 for a complete
description of the register contents.
RESET STATE
RESET STATE
L0S_LATENCY
BIT NUMBER
BIT NUMBER
FIELD NAME
L1_LATENCY
PORT_NUM
PCI register offset:
Register type:
Default value:
ASLPMS
RSVD
MLW
MLS
ACCESS
31
15
0
0
R
R
R
R
R
R
R
Table 4−28. Link Capabilities Register Description
30
14
0
x
Port number. This field indicates port number for the PCI Express link. This field is read-only 00h
indicating that the link is associated with port 0.
Reserved. Returns 00 0000b when read.
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of this field is determined by bits 20:18
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
For an asynchronous reference clock, the value of this field is determined by bits 17:15
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of 011b indicates that the L1 exit latency falls between
256 ns to less than 512 ns.
For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls
between 512 ns to less than 1 µs.
Active state link PM support. This field indicates the level of active state power management that
the bridge supports. The value 11b indicates support for both L0s and L1 through active state
power management.
Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a 1x
PCI Express link.
Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum link
speed of 2.5 Gb/s.
29
13
0
x
9Ch
Read-only
0002 XC11h
28
12
0
x
27
11
0
1
26
10
0
1
25
0
9
0
24
0
8
0
DESCRIPTION
23
0
7
0
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
1
19
0
3
0
18
0
2
0
17
1
1
0
16
0
0
1