XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 124

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.23 VC Resource Status Register (VC0)
5.24 VC Resource Capability Register (VC1)
114
31:24
22:16
15:2
13:8
BIT
BIT
7:0
23
15
14
1
0
SCPS155C
The VC resource status register allows software to monitor the status of the port arbitration table for this VC.
See Table 5−19 for a complete description of the register contents.
The VC resource capability register for VC1 provides information to software regarding the port and arbitration
schemes supported by the bridge. See Table 5−20 for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
PORT_TABLE_STATUS
BIT NUMBER
BIT NUMBER
BIT NUMBER
TBL_OFFSET
FIELD NAME
PORT_ARB_
MAX_TIME_
SWITCHING
ARB_CAP
PCI Express extended register offset:
Register type:
Default value:
PCI Express extended register offset:
Register type:
Default value:
REJECT_
SNOOP
SLOTS
PORT_
RSVD
RSVD
ADV_
VC_PENDING
FIELD NAME
RSVD
Table 5−20. VC Resource Capability Register (VC1) Description
ACCESS
Table 5−19. VC Resource Status Register (VC0) Description
15
31
15
0
0
0
R
R
R
R
R
R
R
14
30
14
0
ACCESS
0
0
Port arbitration table offset. This read-only field returns the value 07h to indicate that the port
arbitration table for this VC begins 112 bytes from the top of the VC capability structure.
Reserved. Returns 0b when read.
Maximum time slots. The read-only field returns the value 111 1111b to indicate that all 128 slots
are supported for time-based WRR.
Reject snoop transactions. This bit only has meaningful context for root ports; therefore, returns 0b
when read.
Advanced packet switching. This read-only bit returns the value 0b to indicate that the use of this
VC is not limited to AS traffic.
Reserved. Return 00 0000b when read.
Port arbitration capability. This 8-bit encoded field indicates support for the various schemes that
are supported for port (secondary PCI device) arbitration. The field is encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR with 256 phases
Bits 6 and 7 = Reserved
The returned value of 11h indicates that hardware-fixed round-robin and time-based WRR with
128 phases are both supported.
RU
RU
R
13
29
13
0
0
0
Reserved. Returns 00 0000 0000 0000b when read.
VC negotiation pending. This bit is asserted when VC negotiation is in progress following
a request by software to enable or disable the VC or at startup for VC0.
Port arbitration table status. This bit is automatically set by hardware when any
modification is made to the port arbitration table entries for this VC within the extended
configuration space. This bit is cleared by hardware after software has requested a port
arbitration table refresh and the refresh has been completed.
12
28
12
0
0
0
11
27
11
0
0
0
10
26
10
0
1
0
16Ah
Read-only
0000h
16Ch
Read-only
077F 0011h
25
9
0
1
9
0
24
8
0
1
8
0
DESCRIPTION
23
DESCRIPTION
7
0
0
7
0
22
6
0
1
6
0
21
5
0
1
5
0
April 2007 Revised October 2008
20
4
0
1
4
1
19
3
0
1
3
0
18
2
0
1
2
0
17
1
0
1
1
0
16
0
0
1
0
1