XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 68

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.18 Memory Base Register
4.19 Memory Limit Register
4.20 Prefetchable Memory Base Register
58
15:4
15:4
15:4
BIT
BIT
BIT
3:0
3:0
3:0
SCPS155C
This read/write register specifies the lower limit of the memory addresses that the bridge forwards
downstream. See Table 4−9 for a complete description of the register contents.
This read/write register specifies the upper limit of the memory addresses that the bridge forwards
downstream. See Table 4−10 for a complete description of the register contents.
This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards
downstream. See Table 4−11 for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
FIELD NAME
FIELD NAME
FIELD NAME
MEMBASE
MEMLIMIT
PREBASE
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
RSVD
RSVD
64BIT
ACCESS
ACCESS
ACCESS
Table 4−11. Prefetchable Memory Base Register Description
15
15
15
0
0
0
RW
RW
RW
R
R
R
14
14
14
0
0
0
Table 4−10. Memory Limit Register Description
Table 4−9. Memory Base Register Description
Memory base. Defines the lowest address of the memory address range that determines when to
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be 00000h.
Reserved. Returns 0h when read.
Memory limit. Defines the highest address of the memory address range that determines when to
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.
Reserved. Returns 0h when read.
Prefetchable memory base. Defines the lowest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.22) specifies
bits [63:32] of the 64-bit prefetchable memory address.
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
13
13
13
0
0
0
20h
Read-only, Read/Write
0000h
22h
Read-only, Read/Write
0000h
24h
Read-only, Read/Write
0001h
12
12
12
0
0
0
11
11
11
0
0
0
10
10
10
0
0
0
9
0
9
0
9
0
8
0
8
0
8
0
DESCRIPTION
DESCRIPTION
DESCRIPTION
7
0
7
0
7
0
6
0
6
0
6
0
5
0
5
0
5
0
April 2007 Revised October 2008
4
0
4
0
4
0
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
0
0
0
0
1