XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 93

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

4.63 Control and Diagnostic Register 2
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.64 Subsystem Access Register
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
April 2007 Revised October 2008
31:24†
23:16†
31:16†
15:13
12:8†
15:0†
4:0†
BIT
BIT
7:6
5:0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−37 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 84h and 86h. See Table 4−38 for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
SubsystemVendorID
FIELD NAME
ASYNC_CLK
COMMON_
LINK_NUM
PHY_REV
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
BAROWE
N_FTS_
N_FTS_
FIELD NAME
SubsystemID
RSVD
RSVD
CLK
ACCESS
31
15
31
15
Table 4−37. Control and Diagnostic Register 2 Description
0
0
0
0
RW
RW
RW
RW
RW
R
R
Table 4−38. Subsystem Access Register Description
ACCESS
30
14
30
14
RW
RW
0
1
0
0
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is the number of FTS that are sent on a transition from
L0s to L0. This field shall default to 32h.
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
4.53) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field defaults to 14h.
PHY revision number
Link number
Reserved. Returns 00b when read.
BAR 0 Write Enable. When this bit is clear (default), the Base Address at offset 10h is read only
and writes to that register will have no effect. When this bit is set, then bits 31:12 of the Base
Address Register becomes writeable allowing the address of the 4K window to the Memory
Mapped TI Proprietary Registers to be changed.
Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00000b.
29
13
29
13
1
1
0
0
Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.45).
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (see Section 4.44).
C8h
Read/Write
3214 6000h
D0h
Read/Write
0000 0000h
28
12
28
12
1
0
0
0
27
27
11
11
0
0
0
0
26
10
26
10
0
0
0
0
25
25
1
9
0
0
9
0
24
24
0
8
0
0
8
0
DESCRIPTION
DESCRIPTION
23
23
0
7
0
0
7
0
22
22
0
6
0
0
6
0
21
21
0
5
0
0
5
0
Classic PCI Configuration Space
20
20
1
4
0
0
4
0
19
19
0
3
0
0
3
0
SCPS155C
18
18
1
2
0
0
2
0
17
17
0
1
0
0
1
0
16
16
0
0
0
0
0
0
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