XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 131

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

6.5
6.6
6.7
April 2007 Revised October 2008
15:4
BIT
3:1
0
Upstream Isochronous Window 0 Control Register
The upstream isochronous window 0 control register allows software to identify the traffic class (TC)
associated with upstream transactions targeting memory addresses in the range defined by the window. See
Table 6−4 for a complete description of the register contents.
Upstream Isochronous Window 0 Base Address Register
The upstream isochronous window 0 base address register allows software to configure the base address for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
Upstream Isochronous Window 0 Limit Register
The upstream isochronous window 0 limit register allows software to configure the upper address bound for
this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the
window is disabled.
ISOC_WINDOW_EN
RESET STATE
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
Device control memory window register offset:
Register type:
Default value:
FIELD NAME
RSVD
TC_ID
Table 6−4. Upstream Isochronous Window 0 Control Register Description
15
31
15
31
15
0
0
0
0
0
ACCESS
RW
RW
14
30
14
30
14
R
0
0
0
0
0
13
29
13
29
13
0
0
0
0
0
Reserved. Returns 000h when read.
Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined
by the associated window must be mapped to. The default value for this field is 000b.
Isochronous window enable.
0 = Address window does not impact upstream traffic (default)
1 = Upstream transactions targeting addresses within the range of this window are applied
12
28
12
28
12
0
0
0
0
0
to the appropriate TC
27
27
11
11
11
0
0
0
0
0
10
26
10
26
10
0
0
0
0
0
25
25
9
0
0
9
0
0
9
0
24
24
08h
Read-only, Read/Write
0000h
8
0
0Ch
Read/Write
0000 0000h
0
8
0
10h
Read/Write
0000 0000h
0
8
0
DESCRIPTION
23
23
Memory-Mapped TI Proprietary Register Space
7
0
0
7
0
0
7
0
22
22
6
0
0
6
0
0
6
0
21
21
5
0
0
5
0
0
5
0
20
20
4
0
0
4
0
0
4
0
19
19
3
0
0
3
0
0
3
0
SCPS155C
18
18
2
0
0
2
0
0
2
0
17
17
1
0
0
1
0
0
1
0
16
16
0
0
0
0
0
0
0
0
121