XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 44

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.5.1.3
3.5.2 PCI Isochronous Windows
34
PCI Express VC extended
configuration registers
1C0h to 1FCh
PCI Express VC extended
configuration register 170h
PCI Express VC extended
configuration register 176h
Device control memory
window register 04h
Device control memory
window register 08h
Device control memory
window register 0Ch
Device control memory
window register 10h
REGISTER OFFSET
REGISTER OFFSET
SCPS155C
To enable the 128-phase, WRR time-based arbiter, two configuration registers must be written. Bit 1
(PORTARB_LEVEL_1_EN) in the upstream isochrony control register at offset 04h (see Section 6.4) within
the device control memory window register map must be asserted. The VC1 resource control register at offset
170h within the PCI Express VC extended configuration space has a PORT_ARB_SELECT field that must
be set to 100b (see Section 5.22).
Table 3−7 identifies and describes the registers associated with 128-phase, WWR time-based arbitration
mode.
The last option for PCI port arbitration is 128-phase, WRR aggressive time-based arbitration mode. This
arbitration mode performs the same as isochronous mode arbitration, but with one difference. When an
isochronous timing event occurs, the PCI bus arbiter deliberately stops a secondary bus master in the middle
of the transaction to assure that isochrony is preserved. The register setup for this arbitration option is the
same as the 128-phase, WRR time-based arbiter option with the following addition. Bit 2
(PORTARB_LEVEL_2_EN) in the device control memory window upstream isochrony control register at offset
04h must be asserted (see Section 6.4).
The bridge has four separate windows that allow PCI bus-initiated memory transactions to be labeled with a
PCI Express traffic class (TC) beyond the default TC0. Each window designates a range of PCI memory space
that is mapped to a specified TC label. This advance feature is configured through the device control memory
window register map.
Table 3−8 identifies and describes the registers associated with isochronous arbitration mode.
128-Phase, WRR Aggressive Time-Based Arbiter
Upstream isochronous window 0
control (see Section 6.5)
Upstream isochronous window 0
base address (see Section 6.6)
Upstream isochronous window 0
limit address (see Section 6.7)
Port arbitration table
(see Section 5.28)
VC1 resource control
(see Section 5.25)
VC1 resource status
(see Section 5.26)
Upstream isochrony
control (see Section 6.4)
Table 3−7. 128-Phase, WRR Time-Based Arbiter Registers
REGISTER NAME
REGISTER NAME
Table 3−8. PCI Isochronous Windows
16-doubleword sized configuration registers that are the registered version of the
128-phase, WRR port arbitration table. Each port arbitration table entry is a 4-bit
field.
Bits 19:17 (PORT_ARB_SELECT) equal to 100b define the port arbitration
mechanism as 128-phase WRR.
Bit 16 (LOAD_PORT_TABLE), when written with a 1b, transfers the port arbitration
table configuration register values to the internal registers used by the PCI bus
arbiter.
Bit 0 (PORT_TABLE_STATUS) equal to 1b indicates that the port arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
Bit 1 (PORTARB_LEVEL_1_EN) must be asserted to enable the 128-phase, WRR
time-based arbiter.
Bits 3:1 (ISOC_WINDOW_EN) indicate that memory addresses within the
base and limit addresses are mapped to a specific traffic class ID.
Bit 0 (TC_ID) identifies the specific traffic class ID.
Note: Memory-mapped register space exists for four upstream windows.
Only window 0 is included in this table.
Window 0 base address
Window 0 limit address
DESCRIPTION
DESCRIPTION
April 2007 Revised October 2008