XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 112

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

PCI Express Extended Configuration Space
5.7
† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
102
31:13
11:9
BIT
12†
5:1
8†
7†
6†
0†
SCPS155C
Correctable Error Mask Register
The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit
is set to 1b, the corresponding error status bit is not set, PCI Express error messages are blocked, the header
log is not loaded, and the first error pointer is not updated. See Table 5−6 for a complete description of the
register contents.
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
REPLAY_TMOUT_MASK
REPLAY_ROLL_MASK
PCI Express extended register offset:
Register type:
Default value:
RX_ERROR_MASK
BAD_DLLP_MASK
BAD_TLP_MASK
FIELD NAME
RSVD
RSVD
RSVD
31
15
0
0
Table 5−6. Correctable Error Mask Register Description
30
14
0
0
ACCESS
29
13
RW
RW
RW
RW
RW
0
0
R
R
R
28
12
0
0
Reserved. Returns 000 0000 0000 0000 0000b when read.
Replay timer time-out mask.
Reserved. Returns 000b when read.
REPLAY_NUM rollover mask.
Bad DLLP error mask.
Bad TLP error mask.
Reserved. Returns 00000b when read.
Receiver error mask.
0 = Error condition is unmasked (default)
1 = Error condition is masked
0 = Error condition is unmasked (default)
1 = Error condition is masked
0 = Error condition is unmasked (default)
1 = Error condition is masked
0 = Error condition is unmasked (default)
1 = Error condition is masked
0 = Error condition is unmasked (default)
1 = Error condition is masked
27
11
0
0
26
10
0
0
114h
Read-only, Read/Write
0000 0000h
25
0
9
0
24
0
8
0
23
0
7
0
DESCRIPTION
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0