XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 106

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Clock Generator Module (CGM)
8.6.4 PLL Reference Divider Select Register (PRDS)
Advance Information
106
NOTE:
NOTE:
Address:
MUL[11:0] — Multiplier select bits
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
The PLL reference divider select register contains the programming
information for the modulo reference divider.
RDS[3:0] — Reference Divider Select Bits
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
Reset:
Read:
Write:
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier N. (See
Programming the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $002 for a default multiply
value of 2.
These read/write bits control the modulo reference divider that selects
the reference division factor R. (See
Programming the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See
initializes the register to $01 for a default divide value of 1.
Figure 8-6. PLL Reference Divider Select Register (PRDS)
$003F
Bit 7
0
0
Clock Generator Module (CGM)
8.4.7 Special Programming
= Unimplemented
6
0
0
PLL.) MUL[11:0] cannot be written when the
PLL.) RDS[7:0] cannot be written when the
5
0
0
4
0
0
8.4.3 PLL Circuits
8.4.3 PLL Circuits
RDS3
3
0
Exceptions.) Reset
MC68HC(7)08KH12
RDS2
2
0
RDS1
1
0
and
and
MOTOROLA
—
8.4.6
8.4.6
Rev. 1.0
RDS0
Bit 0
1