XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 57
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XC68HC08KH12
Manufacturer Part Number
XC68HC08KH12
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC08KH12.pdf
(262 pages)
- Current page: 57 of 262
- Download datasheet (3Mb)
6.4.5 Condition Code Register (CCR)
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic one. The following paragraphs describe
the functions of the condition code register.
V — Overflow Flag
H — Half-Carry Flag
Reset:
Read:
Write:
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The half-
carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
X = Indeterminate
Bit 7
X
V
Central Processor Unit (CPU)
Figure 6-6. Condition Code Register (CCR)
6
1
1
5
1
1
H
X
4
3
1
I
Central Processor Unit (CPU)
N
X
2
Advance Information
X
1
Z
CPU Registers
Bit 0
C
X
57
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