XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 69

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

7.4.2.2 Computer Operating Properly (COP) Reset
MC68HC(7)08KH12
MOTOROLA
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
—
Rev. 1.0
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 2
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1/V
at V
be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1/V
from becoming disabled as a result of external noise. During a break
state, V
CYCLES
4096
DD
+ V
12
DD
Figure 7-7. POR Recovery
System Integration Module (SIM)
– 2
+ V
HI
CYCLES
while the MCU is in monitor mode. The COP module can
4
32
HI
CGMXCLK cycles, drives the COP counter. The COP
on the RST pin disables the COP module.
CYCLES
32
PP
pin. This prevents the COP
$FFFE
System Integration Module (SIM)
Reset and System Initialization
Advance Information
PP
$FFFF
pin is held
69