XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 94

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Clock Generator Module (CGM)
8.4.6 Programming the PLL
Advance Information
94
noise hit and the software must take appropriate action, depending on
the application. (See
using interrupts.) The following conditions apply when the PLL is in
automatic bandwidth control mode:
The following procedure shows how to program the PLL.
1. Choose the desired bus frequency, f
•
•
•
•
•
The ACQ bit (See
(PBWC).) is a read-only indicator of the mode of the filter. (See
8.4.4 Acquisition and Tracking
The ACQ bit is set when the VCO frequency is within a certain
tolerance,
a certain tolerance,
Specifications
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance,
a certain tolerance
Specifications
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See
Control Register
The relationship between the VCO frequency f
frequency f
The VCO frequency need to be at 48MHz for the USB module
reference clock.
Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz,
3MHz, or 1.5MHz respectively.
Clock Generator Module (CGM)
BUS
TRK
LOCK
, and is cleared when the VCO frequency is out of
8.7 Interrupts
is
, and is cleared when the VCO frequency is out of
for more information.)
for more information.)
(PCTL).)
8.6.2 PLL Bandwidth Control Register
UNL
UNT
. (See
48MHz
------------------- -
. (See
f
-------------
2
VCLK
2
P
P
for information and precautions on
8.9 Acquisition/Lock Time
8.9 Acquisition/Lock Time
=
=
4 f
4 f
Modes.)
BUS
BUS
BUS
MC68HC(7)08KH12
.
VCLK
and the bus
8.6.1 PLL
MOTOROLA
—
Rev. 1.0