XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 68

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

System Integration Module (SIM)
7.4.2.1 Power-On Reset
Advance Information
68
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur. At power-on, the following events occur:
CGMXCLK
•
•
•
•
•
•
IRST
RST
IAB
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive CGMXCLK.
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
System Integration Module (SIM)
Figure 7-6. Sources of Internal Reset
Figure 7-5. Internal Reset Timing
ILLEGAL ADDRESS RST
RST PULLED LOW BY MCU
ILLEGAL OPCODE RST
32 CYCLES
COPRST
POR
USB
INTERNAL RESET
32 CYCLES
MC68HC(7)08KH12
VECTOR HIGH
MOTOROLA
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Rev. 1.0