XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 211

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

13.5 COP Control Register (COPCTL)
13.6 Interrupts
13.7 Monitor Mode
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
Address:
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
IRQ1/V
Reset:
Read:
Write:
COPRS selects the COP timeout period. Reset clears COPRS.
COPD disables the COP module.
1 = COP reset cycle is (2
0 = COP reset cycle is (2
1 = COP module disabled
0 = COP module enabled
PP
$FFFF
Computer Operating Properly (COP)
Bit 7
pin or on the RST pin.
Figure 13-3. COP Control Register (COPCTL)
6
5
13
18
Low byte of reset vector
Unaffected by reset
Clear COP counter
–2
–2
4
4
4
) CGMXCLK
) CGMXCLK
Computer Operating Properly (COP)
3
COP Control Register (COPCTL)
DD
+ V
2
HI
is present on the
Advance Information
1
Bit 0
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