XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 93

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

8.4.4 Acquisition and Tracking Modes
8.4.5 Manual and Automatic PLL Bandwidth Modes
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
The PLL filter is manually or automatically configurable into one of two
operating modes:
This CGM is optimized for Automatic PLL Bandwidth Mode, and is the
mode recommended for most users.
In automatic bandwidth control mode (AUTO=1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software
can poll the LOCK bit continuously (during PLL startup, usually) or at
periodic intervals. In either case, when the LOCK bit is set, the VCO
clock is safe to use as the source for the base clock. (See
Clock Selector
base clock and the LOCK bit is clear, the PLL has suffered a severe
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Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See
(PBWC).)
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
Clock Generator Module (CGM)
Circuit.) If the VCO is selected as the source for the
8.6.2 PLL Bandwidth Control Register
8.4.8 Base Clock Selector
8.6.2 PLL Bandwidth Control Register
Clock Generator Module (CGM)
Circuit.) The PLL is
Functional Description
Advance Information
8.4.8 Base
(PBWC).) If
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