XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 194

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

I/O Ports
Advance Information
194
NOTE:
Address:
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
When bit DDRDx is a logic one, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
the operation of the port D pins.
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
Figure 12-12
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
$0007
Bit 7
Figure 12-11. Data Direction Register D (DDRD)
0
DDRD6
shows the port D I/O logic.
6
0
Figure 12-12. Port D I/O Circuit
I/O Ports
RESET
DDRD5
5
0
DDRD4
DDRDx
PTDx
4
0
DDRD3
3
0
MC68HC(7)08KH12
Table 12-5
DDRD2
2
0
DDRD1
summarizes
1
0
MOTOROLA
—
DDRD0
Rev. 1.0
Bit 0
0
PTDx