KFM2G16Q2M-DEB5 SAMSUNG [Samsung semiconductor], KFM2G16Q2M-DEB5 Datasheet - Page 8

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KFM2G16Q2M-DEB5

Manufacturer Part Number
KFM2G16Q2M-DEB5
Description
MuxOneNAND FLASH MEMORY
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
1.6
MuxOneNAND
trol logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and
4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed
of ~76ns.
The device operates up to a maximum host-driven clock frequency of 54MHz for synchronous reads at Vcc(or Vccq. Refer to chapter
4.2) with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are deter-
mined by programmable read latency.
MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter
register. The device includes one block-sized OTP (One Time Programmable) area that can be used to increase system security or
to provide identification capabilities.
General Overview
‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes con-
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FLASH MEMORY

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