Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 103

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
[6:5]
TICONFIG
[4]
[3:1]
PWMD
[0]
INPCAP
Bit
Field
RESET
R/W
Address
Bit
[7]
TEN
Description
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
Description (Continued)
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.
10 = Timer Interrupt only on defined Input Capture/Deassertion Events.
11 = Timer Interrupt only on defined Reload/Compare Events.
Reserved
This bit is reserved and must be programmed to 0.
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event.
1 = Previous timer interrupt is a result of Timer Input Capture Event.
TEN
R/W
7
0
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers, shown in Table 51, enable and disable the
timers, set the prescaler value and determine the timer operating mode.
TPOL
R/W
Table 51. Timer 0–1 Control Register 1 (TxCTL1)
6
0
R/W
5
0
P R E L I M I N A R Y
PRES
R/W
4
0
F07H, F0FH
R/W
3
0
Z8 Encore! XP
Timer Control Register Definitions
R/W
2
0
Product Specification
TMODE
R/W
1
0
®
F082A Series
R/W
0
0
86