Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 69
Z8F041APH020SG2156
Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F082ASJ020EG2156.pdf
(282 pages)
Specifications of Z8F041APH020SG2156
Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS022827-1212
Bit
[7:0]
PxIN
Note: x indicates the specific GPIO port pin number (7–0).
Bit
Field
RESET
R/W
Address
Bit
[7:0]
PxOUT
Note: x indicates the specific GPIO port pin number (7–0).
Bit
Field
RESET
R/W
Address
X = Undefined.
Port A–C Input Data Registers
Port A–D Output Data Register
Description
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Description
Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the corre-
sponding pin is configured as an output and the pin is not configured for alternate function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
POUT7
PIN7
R/W
the corresponding Port Output Control Register bit to 1.
R
X
7
7
0
Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled
values from the corresponding port pins. The Port A–C Input Data registers are read-only.
The value returned for any unused ports is 0. Unused ports include those missing on the 8-
and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins.
POUT6
PIN6
R/W
Table 30. Port A–D Output Data Register (PxOUT)
R
6
X
6
0
Table 29. Port A–C Input Data Registers (PxIN)
POUT5
PIN5
R/W
X
R
5
5
0
P R E L I M I N A R Y
FD3H, FD7H, FDBH, FDFH
FD2H, FD6H, FDAH
POUT4
PIN4
R/W
R
X
4
4
0
POUT3
PIN3
R/W
X
R
3
3
0
Z8 Encore! XP
GPIO Control Register Definitions
POUT2
PIN2
R/W
R
X
2
2
0
Product Specification
POUT1
PIN1
R/W
X
R
1
1
0
®
F082A Series
POUT0
PIN0
R/W
R
X
0
0
0
52
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