Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 63
Z8F041APH020SG2156
Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F082ASJ020EG2156.pdf
(282 pages)
Specifications of Z8F041APH020SG2156
Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7:0]
PCTLx
Note: x indicates the specific GPIO port pin number (7–0).
Bit
Field
RESET
R/W
Address
Bit
[7:0]
DDx
Note: x indicates the specific GPIO port pin number (7–0).
Port A–D Control Registers
Port A–D Data Direction Subregisters
Description
Port Control
The Port Control Register provides access to all subregisters that configure the GPIO port
operation.
Description
Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register.
R/W
DD7
R/W
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
The output driver is tristated.
7
7
1
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address Register determines which subregister is read from or written to by
a Port A–D Control Register transaction; see Table 20.
The Port A–D Data Direction subregister is accessed through the Port A–D Control Regis-
ter by writing
Table 21. Port A–D Data Direction Subregisters (PxDD)
DD6
R/W
R/W
6
6
1
Table 20. Port A–D Control Registers (PxCTL)
01H
to the Port A–D Address Register; see Table 21.
R/W
DD5
R/W
5
5
1
P R E L I M I N A R Y
FD1H, FD5H, FD9H, FDDH
DD4
R/W
R/W
4
4
1
PCTL
00H
R/W
DD3
R/W
3
3
1
Z8 Encore! XP
GPIO Control Register Definitions
DD2
R/W
R/W
2
2
1
Product Specification
R/W
DD1
R/W
1
1
1
®
F082A Series
DD0
R/W
R/W
0
0
1
46
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