Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 139

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Baud Rate
IR_RXD
UART’s
Clock
RXD
Caution:
Receiving IrDA Data
8 clock
delay
Start Bit = 0
Data received from the infrared transceiver using the IR_RXD signal through the RXD pin
is decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 displays data reception.
When the infrared endec is enabled, the UART’s RXD signal is internal to the Z8 Encore!
XP F082A Series products while the IR_RXD signal is received through the RXD pin.
Infrared Data Reception
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
16 clock
The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.4 µs minimum width pulses allowed by the IrDA standard.
min. 1.4
period
pulse
Start Bit = 0

16 clock
s
period
Data Bit 0 = 1
Figure 18. IrDA Data Reception
Data Bit 0 = 1
P R E L I M I N A R Y
16 clock
period
Data Bit 1 = 0
Data Bit 1 = 0
16 clock
period
Data Bit 2 = 1
Z8 Encore! XP
Data Bit 2 = 1
16 clock
period
Product Specification
Data Bit 3 = 1
®
F082A Series
Data Bit 3 = 1
Operation
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