Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 195

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Byte Read
Power Failure Protection
Optimizing NVDS Memory Usage for Execution Speed
To read a byte from the NVDS array, user code must first push the address onto the stack.
User code issues a
the return from the sub-routine, the read byte resides in working register R0 and the read
status byte resides in working register R1. The contents of the status byte are undefined for
read operations to illegal addresses. Also, the user code must pop the address byte off the
stack.
The read routine uses 9 bytes of stack space in addition to the one byte of address pushed
by the user. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS reads exhibit a nonuniform execution
time. A read operation takes between 44 s and 489 s (assuming a 20 MHz system
clock). Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 2 s execution time.
The status byte returned by the NVDS read routine is zero for successful read, as deter-
mined by a CRC check. If the status byte is nonzero, there was a corrupted value in the
NVDS array at the location being read. In this case, the value returned in R0 is the byte
most recently written to the array that does not have a CRC error.
The NVDS routines employ error checking mechanisms to ensure a power failure endan-
gers only the most recently written byte. Bytes previously written to the array are not per-
turbed.
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
NVDS read time can vary drastically. This discrepancy is a trade-off for minimizing the
frequency of writes that require post-write page erases, as indicated in Table 107. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N, plus the number of writes since the most recent
page erase. Neglecting effects caused by page erases and results caused by the initial con-
dition in which the NVDS is blank, a rule of thumb is that every write since the most
recent page erase causes read times of unwritten addresses to increase by 1 s up to a max-
imum of (511-NVDS_SIZE) s.
CALL
instruction to the address of the byte-read routine (
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
NVDS Code Interface
®
F082A Series
0x1000
). At
178