Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 95

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
delay ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and
initiating the PWM operation:
1. Write to the Timer Control Register to:
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control Register to set the PWM dead band delay value. The dead-
5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
7. Configure the associated GPIO port pin for the Timer Output and Timer Output Com-
8. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than
registers, the ONE-SHOT Mode equation determines the first PWM time-out period.
PWM Period (s)
–
–
–
–
cally
in PWM mode, counting always begins at the reset value of
band delay must be less than the duration of the positive phase of the PWM signal (as
defined by the PWM high and low byte registers). It must also be less than the dura-
tion of the negative phase of the PWM signal (as defined by the difference between
the PWM registers and the Timer Reload registers).
period). The reload value must be greater than the PWM value.
to the relevant interrupt registers.
plement alternate functions. The Timer Output Complement function is shared with
the Timer Input function for both timers. Setting the timer mode to Dual PWM auto-
matically switches the function from Timer In to Timer Out Complement.
Disable the timer
Configure the timer for PWM DUAL OUTPUT Mode by writing the TMODE
bits in the TxCTL1 Register and the TMODEHI bit in TxCTL0 Register
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
0001H
). This only affects the first pass in PWM mode. After the first timer reset
=
------------------------------------------------------------------------------ -
System Clock Frequency (Hz)
Reload Value xPrescale
P R E L I M I N A R Y
0001H
is loaded into the Timer High and Low Byte
Z8 Encore! XP
Product Specification
0001H
.
®
F082A Series
Operation
78